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1 of 49 december 2004 ? 2004 integrated device technology, inc. all rights reserved. product specification subject to change without notice. dsc 6029/1 idt and the idt logo are registered trademarks of integrated device technology, inc. quad port phy (physical layer) for 25.6, 51.2, and 204.8 mbps atm networks and backplane applications features list ! performs the phy-transmission convergence (tc) and physical media dependent (pmd) sublayer functions for four 204.8 mbps atm channels ! compliant to atm forum (af-phy-040.000) and itu-t i.432.5 specifications for 25.6 mbps physical interface ! operates at 25.6, 51.2, 102.4, 204.8 mbps data rates ! individual selection of port data rates ! backwards compatible with 77v1254l25 ! utopia level 1, utopia level 2, or dpi-4 interface ! 3-cell transmit and receive fifos ! led interface for status signalling ! supports utp category 3 and 5 physical media ! low-power cmos ! 3.3v supply with 5v tolerant inputs ! 144-pin pqfp package (28 x 28 mm) ! industrial temperature ranges description the IDT77V1264l200 is a member of idt's family of products supporting asynchronous transfer mode (atm) data communications and networking. the IDT77V1264l200 implements the physical layer for 25.6 mbps atm, connecting four seri al copper links (utp category 3 and 5) to one atm layer device such as a sar or a switch asic. the IDT77V1264l200 also operates at 51.2 mbps and 204.8 mbps, and is well suited to backplane driving applications. the 77v1264l200-atm layer interface is selectable as either: 16-bit utopia level 2, 8-bit utopia level 1 multi-phy, or quadruple 4-bit dpi (data path interface). the IDT77V1264l200 is fabricated using idt's state-of-the-art cmos technology, providing the highest levels of integration, perfor- mance and reliability, with the low-power consumption characteristics of cmos. block diagram rxclk clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx 0 rx 0 clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx 1 rx 1 clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx 2 rx 2 clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx 3 rx 3 phy-atm interface (utopia or dpi) microprocessor interface txdata[15:0] txclk txen rxdata[15:0] rxen 4 4 rxled[3:0] txled[3:0] rxref txref txaddr[4:0] rxaddr[4:0] + - + - + - + - + - + - txsoc txclav txparity mode[1:0] rxsoc rxclav rxparity 3505 drw 01 + - + - int rst rd wr ale ad[7:0] cs osc driver driver driver driver . IDT77V1264l200
2 of 49 december 2004 IDT77V1264l200 applications ! up to 204.8mbps backplane transmission ! rack-to-rack short links ! atm switches 77v1264l200 overview the 77v1264l200 is a four port implementation of the physical layer standard for 25.6mbps atm network communications as defined by atm forum document af-phy-040.000 and itu-t i.432.5. the physical layer is divided into a physical media dependent sub layer (pmd) and transmission convergence (tc) sub layer. the pmd sub layer includes the functions for the transmitter, receiver and clock recovery for opera- tion across 100 meters of category 3 and 5 unshielded twisted pair (utp) cable. this is referred to as the line side interface. the tc sub layer defines the line coding, scrambling, data framing and synchroniza- tion. on the other side, the 77v1264l200 interfaces to an atm layer device (such as a switch core or sar). this cell level interface is config- urable as either an 8-bit utopia level 1 multi-phy, 16-bit utopia level 2, or four 4-bit dpi interface, as determined by two mode pins. this is referred to as the phy-atm interface. the pinout and front page block diagram are based on the utopia 2 c onfiguration. table 3 shows the corresponding pin functions for the other two modes, and figure 2 and figure 3 show functional block diagrams. the 77v1264l200 is based on the 77105, and maintains significant register compatibility with it. the 77v1264l200, however, has additional register features, and also duplicates most of its registers to provide significant independence between the four ports. access to these status and control registers is through the utility bus. this is an 8-bit muxed address and data bus, controlled by a conven- tional asynchronous read/write handshake. additional pins permit insertion and extraction of an 8khz timing marker, and provide led indication of receive and transmit status. auto-synchronization and good signal indica- tion the 77v1264l200 features a new receiver synchronization algorithm that allow it to achieve 4b/5b symbol framing on any valid data stream. this is an improvement on earlier products which could frame only on the escape symbol, which occurs only in start-of-cell or 8khz (x8) timing marker symbol pairs. atm25 transceivers always transmit valid 4b/5b symbols, allowing the 77v1264l200 receive section to achieve symbol framing and prop- erly indicate receive signal status, even in the absence of atm cells or 8khz (x8) timing markers in the receive data stream. a state machine monitors the received symbols and asserts the ?good signal? status bit when a valid signal is being received. ?good signal? is deasserted and the receive fifo is disabled when the signal is lost. this is sometimes referred to as loss of signal (los). operation at speeds above 25 mbps in addition to operation at the standard rate of 25.6 mbps, the 77v1264l200 can be operated at a range of data rates, up to 204.8 mbps, as shown in table 3. for 204.8mbps data rate applications, st6200t magnetics from pulse engineering can be used. these magnetics have been tested to work over 10 meters of utp 5 cable at 204.8mbps. the rate is determined by the frequency of the osc clock, multiplied by the internal pll clock multiplier factor (1x, 2x or 4x) as determined in the enhanced control 2 registers. although the osc clock frequency is common to all ports of the phy, the clock multiplier factor can be set individually for each port. as an example, with a 64 mhz oscillator, this allows some ports to operate at 51.2 mbps while other ports are simultaneously operating at 204.8 mbps. when operating at clock multiples other than 1x, use of the rxref pin requires that the rxref pulse width select field in the led driver and hec status/control registers be programmed to a value greater than the default of 1 cycle. also, the phy loopback mode without clock recovery (10) in the diagnostic control registers works only when the clock multiplier is 1x. for higher multiples, the phy loopback mode (01) with clock recovery must be used. except as noted above, these higher speed configurations operate exactly the same as the basic 25.6 mbps configuration. the scrambling and encoding are unchanged. table 1 shows some of the different data rates the phy can operate at with a 32mhz or 64mhz oscillator. note that any oscillator frequency between 32mhz and 64mhz can be used. for example, if a 48mhz oscillator is used and the multiplier is set to 4x, the data rate would be 153.6mbps. reference clock (osc) clock multiplier control bits (enhanced control 2 registers) line bit rate (mhz) data rate (mbps) 32 mhz 00 (1x) 32 25.6 01 (2x) 64 51.2 10 (4x) 128 102.4 64 mhz 00 (1x) 64 51.2 01 (2x) 128 102.4 10 (4x) 256 204.8 table 1 200 speed grade option
3 of 49 december 2004 IDT77V1264l200 figure 1 pin assignments vdd gnd tx0- tx0+ vdd mm mode1 mode0 rxref txref gnd txled3 txled2 txled1 txled0 vdd txdata0 txdata1 txdata2 txdata3 txdata4 txdata5 txdata6 txdata7 txdata8 txdata9 txdata10 txdata11 txdata12 txdata13 txdata14 txdata15 txparity txen txsoc txaddr4 t x a d d r 3 v d d t x a d d r 2 t x a d d r 1 t x a d d r 0 t x c l a v t x c l k g n d v d d r x c l k r x e n r x a d d r 0 r x a d d r 1 g n d r x a d d r 2 r x a d d r 3 r x a d d r 4 r x c l a v r x s o c g n d v d d r x p a r i t y r x d a t a 1 5 r x d a t a 1 4 r x d a t a 1 3 r x d a t a 1 2 r x d a t a 1 1 r x d a t a 1 0 r x d a t a 9 r x d a t a 8 g n d v d d r x d a t a 7 r x d a t a 6 r x d a t a 5 r x d a t a 4 vdd gnd tx3+ tx3- vdd da se ad7 ad6 ad5 ad4 gnd ad3 ad2 ad1 ad0 vdd ale cs rd wr rst gnd int vdd gnd rxled3 rxled2 rxled1 rxled0 vdd gnd rxdata0 rxdata1 rxdata2 rxdata3 o s c t x 1 + t x 1 - g n d a g n d a v d d r x 0 + r x 0 - a v d d a g n d a g n d a v d d r x 1 + r x 1 - a v d d a g n d a g n d a v d d a g n d a v d d a g n d a g n d a v d d r x 2 + r x 2 - a v d d a g n d a g n d a v d d r x 3 + r x 3 - a v d d a g n d g n d t x 2 + t x 2 - 1 4 4 1 4 3 1 4 2 1 4 1 1 4 0 1 3 9 1 3 8 1 3 7 1 3 6 1 3 5 1 3 4 1 3 3 1 3 2 1 3 1 1 3 0 1 2 9 1 2 8 1 2 7 1 2 6 1 2 5 1 2 4 1 2 3 1 2 2 1 2 1 1 2 0 1 1 9 1 1 8 1 1 7 1 1 6 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 1 0 9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 77v1254 144-pqfp 3505 drw 02 . 77v1264l200
4 of 49 december 2004 IDT77V1264l200 signal descriptions line side signals signal name pin number i/o signal description rx0+,- 139, 138 in port 0 positive and negative receive differential input pair. rx1+,- 133, 132 in port 1 positive and negative receive differential input pair. rx2+,- 121, 120 in port 2 positive and negative receive differential input pair. rx3+,- 115, 114 in port 3 positive and negative receive differential input pair. tx0+,- 4, 3 out port 0 positive and negative transmit differential output pair. tx1+,- 144, 143 out port 1 positive and negative transmit differential output pair. tx2+,- 110, 109 out port 2 positive and negative transmit differential output pair. tx3+,- 106, 105 out port 3 positive and negative transmit differential output pair. utility bus signals signal name pin number i/o signal description ad[7:0] 101, 100, 99, 98, 96, 95, 94, 93 in/out utility bus address/data bus. the address input is sampled on the falling edge of ale. data is output on this bus when a read is performed. input data is sampled at the completion of a write operation. ale 91 in utility bus address latch enable. asynchronous input. an address on the ad bus is sampled on the falling edge of ale. ale must be low when the ad bus is being used for data. cs 90 utility bus asynchronous chip select. cs must be asserted to read or write an internal register. it may remain asserted at all times if desired rd 89 in utility bus read enable. active low asynchronous input. after latching an address, a read is performed by deasserting wr and asserting rd and cs . wr 88 in utility bus write enable. active low asynchronous input. after latching an address, a write is performed by deasserting rd , placing data on the ad bus, and asserting wr and cs . data is sampled when wr or cs is deasserted. miscellaneous signals signal name pin number i/o signal description da 103 in reserved signal. this input must be connected to logic low. int 85 out interrupt. int is an open-drain output, driven low to indicate an interrupt. once low, int remains low until the interrupt status in the appropriate interrupt status register is read. interrupt sources are programmable via the interrupt mask registers. mm 6 in reserved signal. this input must be connected to logic low. mode[1:0] 7, 8 in mode selects. they determine the configuration of the phy/atm interface. 00 = utopia level 2. 01 = uto- pia level 1. 10 = dpi. 11 is reserved. osc 126 in ttl line rate clock source, driven by a 100 ppm oscillator. 32 mhz or 64 mhz. rst 87 in reset. active low asynchronous input resets all control logic, counters and fifos. a reset must be per- formed after power up prior to normal operation of the part. rxled[3:0] 82, 81, 80, 79 out receive led drivers. driven low for 223 cycles of osc, beginning with rxsoc when that port receives a good (non-null and non-errored) cell. drives 8 ma both high and low. one per port. rxref 9 out receive reference. active low, synchronous to osc. rxref pulses low for a programmable number of clock cycles when an x_8 command byte is received. register 0x40 is programmed to indicate which port is referenced. note that when operating the 77v1264l200 at 2x or 4x multiple of osc (see enhanced control 2 registers) the rxref pulse width (see led driver and hec status/control registers) must be pro- grammed to any value greater than the default for proper operation of rxref . table 2 signal descriptions (part 1 of 3)
5 of 49 december 2004 IDT77V1264l200 se 102 in reserved signal. this input must be connected to logic low. txled[3:0] 12, 13, 14, 15 out ports 3 through 0 transmit led driver. goes low for 223 cycles of osc, beginning with txsoc when thi s port receives a cell for transmission. 8 ma drive current both high and low. one per port. txref 10 in transmit reference. synchronous to osc. on the falling edge, an x_8 command byte is inserted into the transmit data stream. logic for this signal is programmed in register 0x40. typical application is wan timing. power supply signals signal name pin number i/o signal description agnd 112, 117, 118, 123, 124, 127, 129, 130, 135, 136, 141 ____ analog ground. agnd supply a ground reference to the analog portion of the ship, which sources a more constant current than the digital portion. avdd 113, 116, 119, 122, 125, 128, 131, 134, 137, 140 ____ analog power supply 3.3 0.3v avdd supply power to the analog portion of the chip, which draws a more constant current than the digital portion. gnd 2, 11, 44, 50, 56, 67, 77, 83, 86, 97, 107, 111, 142 ____ digital ground. vdd 1, 5, 16, 38, 45, 57, 68, 78, 84, 92, 104, 108 ____ digital power supply. 3.3 0.3v. 16-bit utopia 2 signals (mode[1:0] = 00) signal name pin number i/o signal description rxaddr[4:0] 53, 52, 51, 49, 48 in utopia 2 receive address bus. this bus is used in polling and selecting the receive port. the po rt addresses are defined in bits [4:0] of the enhanced control registers. rxclav 54 out utopia 2 receive cell available. indicates the cell available status of the addressed port. it is asserted when a full cell is available for retrieval from the receive fifo. when non of the four ports is addressed. rxclav is high impedance. rxclk 46 in utopia 2 receive clock. this is a free running clock input. rxdata[15:0] 59, 60, 61, 62, 63, 64, 65, 66, 69, 70, 71, 72, 73, 74, 75, 76 out utopia 2 receive data. when one of the four ports is selected, the 77v1264l200 transfers received cells to an atm device across this bus. also see rxparity. rxen 47 in utopia 2 receive enable. driven by an atm device to indicate its ability to receive data across the rxdata bus. rxparity 58 out utopia 2 receive data pa rity. odd parity over rxdata[15:0]. rxsoc 55 out utopia 2 receive start of cell. asserted coincident with the first word of data for each cell on rxdata. txaddr[4:0] 36, 37, 39, 40, 41 in utopia 2 transmit address bus. this bus is used in polling and selecting the transmit port. the port addresses are defined in bits [4:0] of the enhanced control registers. txclav 42 out utopia 2 transmit cell available. indicates the availability of room in the transmit fifo of the addressed port for a full cell. when none of the four ports is addressed, txclav is high impedance. txclk 43 in utopia transmit clock. this is a free running clock input. txdata[15:0] 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17 in utopia 2 transmit data. an atm device transfers cells across this bus to the 77v1264l200 for transmission. also see txparity. txen 34 in utopia 2 transmit enable. driven by an atm device to indicate it is transmitting data across the txdata bus. txparity 33 in utopia 2 transmit data parity. odd parity across txdata[15:0]. pari ty is checked and errors are indicated in the interrupt status registers, as enabled in the master control registers. no other action is taken in the event of an error. tie high or low if unused. txsoc 35 in utopia 2 transmit start of cell. asserted coincident with the first word of data for each cell on txdata. table 2 signal descriptions (part 2 of 3)
6 of 49 december 2004 IDT77V1264l200 8-bit utopia level 1 signals (mode[1:0] = 01) signal name pin number i/o signal description rxclav[3:0] 64, 65, 66, 54 out utopia 1 receive cell available. indicates the cell available status of the respective port. it is asserted when a full cell is available for retrieval from the receive fifo. rxclk 46 in utopia 1 receive clock. this is a free running clock input. rxdata[7:0] 69, 70, 71, 72, 73, 74, 75, 76 out utopia 1 receive data. when one of the four ports is selected, the 77v1264l200 tran sfers received cells to an atm device across this bus. bit 5 in the diagnostic control registers determines whether rxdata tri- states when rxen [3:0] are high. also see rxparity. rxen [3:0] 51, 49, 48, 47 in utopia 1 receive enable. driven by an atm device to indicate its ability to receive data across the rxdata bus. one for each port rxparity 58 out utopia 1 receive data pa rity. odd parity over rxdata[7:0]. rxsoc 55 out utopia 1 receive start of cell. asserted coincident with the first word of data for each cell on rxdata. tri- statable as determined by bit 5 in the diagnostic control registers. txclav[3:0] 39, 40, 41, 42 out utopia 1 transmit cell available. indicates the availability of room in the transmit fifo of the re spective port for a full cell. txclk 43 in utopia 1 transmit clock. this is a free running clock input. txdata[7:0] 24, 23, 22, 21, 20, 19, 18, 17 in utopia 1 transmit data. an atm device transfers cells across the bus to the 77v1264l 200 for transmission. also see txparity. txen [3:0] 27, 26, 25, 34 in utopia 1 transmit enable. driven by an atm device to indicate it is transmitting data across the txdata bus. one for each port. txparity 33 in utopia 1 transmit data parity. odd parity across txdata[7:0]. pari ty is checked and errors are indicated in the interrupt status registers, as enabled in the master control registers. no other action is taken in the event of an error. tie high or low if unused. txsoc 35 in utopia 1 transmit start of cell. asserted coincident with the first word of data for each cell on txdata. dpi mode signals (mode[1:0] = 10) signal name pin number i/o signal description dpiclk 43 in dpi source clock for transmit. this is the free-running clock used as the source to generate pn_tclk. pn_rclk 52, 51, 49, 48 in dpi port ?n? receive clock. pn_rclk is cycled to indicate that the interfacing device is ready to receiv e a nibble of data on pn_rd[3:0] of port ?n?. pn_rd[3:0] 59, 60, 61, 62, 63, 64, 65, 66, 69, 70, 71, 72, 73, 74, 75, 76 out dpi port ?n? receive data. cells received on port ?n? are passed to the interfacing device across this bus. each port has its own dedicated bus. pn_rfrm 53, 58, 54, 55 out dpi port ?n? receive frame. pn_rfrm is asserted for one cycle immediately preceding the transfer of eac h cell on pn_rd[3:0]. pn_tclk 37, 39, 40, 41 out dpi port ?n? transmit clock. pn_tclk is derived from dpiclk and is cycled when the respective port is ready to accept another 4 bits of data on pn_td[3:0]. pn_td[3:0] 32, 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, 18, 17 in dpi port ?n? transmit data. cells are passed across this bus to the phy for transmission on port ?n?. each port has its own dedicated bus. pn_tfrm 36, 33, 34, 35 in dpi port ?n? transmit frame. start of cell signal which is asserted for one cycle immediately preceding the first 4 bits of each cell on pn_td[3:0]. table 2 signal descriptions (part 3 of 3)
7 of 49 december 2004 IDT77V1264l200 signal assignment as a function of phy/atm interface mode signal name pin number 16-bit utopia 2 mode[1,0] = 00 8-bit utopia 1 mode[1,0] = 01 dpi mode[1,0] = 10 vdd 1 gnd 2 tx0- 3 tx0+ 4 vdd 5 mm 6 mode1 7 mode0 8 rxref 9 txref 10 gnd 11 txled3 12 txled2 13 txled1 14 txled0 15 vdd 16 txdata0 17 txdata0 txdata0 p0_td[0] txdata1 18 txdata1 txdata1 p0_td[1] txdata2 19 txdata2 txdata2 p0_td[2] txdata3 20 txdata3 txdata3 p0_td[3] txdata4 21 txdata4 txdata4 p1_td[0] txdata5 22 txdata5 txdata5 p1_td[1] txdata6 23 txdata6 txdata6 p1_td[2] txdata7 24 txdata7 txdata7 p1_td[3] txdata8 25 txdata8 txen [1] p2_td[0] txdata9 26 txdata9 txen [2] p2_td[1] txdata10 27 txdata10 txen [3] p2_td[2] txdata11 28 txdata11 see note 2 p2_td[3] txdata12 29 txdata12 see note 2 p3_td[0] txdata13 30 txdata13 see note 2 p3_td[1] txdata14 31 txdata14 see note 2 p3_td[2] txdata15 32 txdata15 see note 2 p3_td[3] txparity 33 txparity txparity p2_tfrm txen 34 txen txen [0] p1_tfrm txsoc 35 txsoc txsoc p0_tfrm txaddr4 36 txaddr4 see note 2 p3_tfrm table 3 signal assignment as a function of phy/atm interface mode (part 1 of 4)
8 of 49 december 2004 IDT77V1264l200 txaddr3 37 txaddr3 see note 2 p3_tclk vdd 38 txaddr2 39 txaddr2 txclav[3] p2_tclk txaddr1 40 txaddr1 txclav[2] p1_tclk txaddr0 41 txaddr0 txclav[1] p0_tclk txclav 42 txclav txclav[0] see note 1 txclk 43 txclk txclk dpiclk gnd 44 vdd 45 rxclk 46 rxclk rxclk see note 2 rxen 47 rxen rxen [0] see note 2 rxaddr0 48 rxaddr0 rxen [1] p0_rclk rxaddr1 49 rxaddr1 rxen [2] p1_rclk gnd 50 rxaddr2 51 rxaddr2 rxen [3] p2_rclk rxaddr3 52 rxaddr3 see note 2 p3_rclk rxaddr4 53 rxaddr4 see note 2 p3_rfrm rxclav 54 rxclav rxclav[0] p1_rfrm rxsoc 55 rxsoc rxsoc p0_frm gnd 56 vdd 57 rxparity 58 rxparity rxparity p2_rfrm rxdata15 59 rxdata15 see note 1 p3_rd[3] rxdata14 60 rxdata14 see note 1 p3_rd[2] rxdata13 61 rxdata13 see note 1 p3_rd[1] rxdata12 62 rxdata12 see note 1 p3_rd[0] rxdata11 63 rxdata11 see note 1 p2_rd[3] rxdata10 64 rxdata10 rxclav[3] p2_rd[2] rxdata9 65 rxdata9 rxclav[2] p2_rd[1] rxdata8 66 rxdata8 rxclav[1] p2_rd[0] gnd 67 vdd 68 rxdata7 69 rxdata7 rxdata7 p1_rd[3] rxdata6 70 rxdata6 rxdata6 p1_rd[2] rxdata5 71 rxdata5 rxdata5 p1_rd[1] rxdata4 72 rxdata4 rxdata4 p1_rd[0] rxdata3 73 rxdata3 rxdata3 p0_rd[3] signal name pin number 16-bit utopia 2 mode[1,0] = 00 8-bit utopia 1 mode[1,0] = 01 dpi mode[1,0] = 10 table 3 signal assignment as a function of phy/atm interface mode (part 2 of 4)
9 of 49 december 2004 IDT77V1264l200 rxdata2 74 rxdata2 rxdata2 p0_rd[2] rxdata1 75 rxdata1 rxdata1 p0_rd[1] rxdata0 76 rxdata0 rxdata0 p0_rd[0] gnd 77 vdd 78 rxled0 79 rxled1 80 rxled2 81 rxled3 82 gnd 83 vdd 84 int 85 gnd 86 rst 87 wr 88 rd 89 cs 90 ale 91 vdd 92 ad0 93 ad1 94 ad2 95 ad3 96 gnd 97 ad4 98 ad5 99 ad6 100 ad7 101 se 102 da 103 vdd 104 tx3- 105 tx3+ 106 gnd 107 vdd 108 tx2- 109 tx2+ 110 signal name pin number 16-bit utopia 2 mode[1,0] = 00 8-bit utopia 1 mode[1,0] = 01 dpi mode[1,0] = 10 table 3 signal assignment as a function of phy/atm interface mode (part 3 of 4)
10 of 49 december 2004 IDT77V1264l200 note: 1.this output signal is unused in this mode. it must be left unconnected. 2.this input signal is unused in this mode. it mu st be connected to either logic high or logic low. gnd 111 agnd 112 avdd 113 rx3- 114 rx3+ 115 avdd 116 agnd 117 agnd 118 avdd 119 rx2- 120 rx2+ 121 avdd 122 agnd 123 agnd 124 avdd 125 osc 126 agnd 127 avdd 128 agnd 129 agnd 130 avdd 131 rx1- 132 rx1+ 133 avdd 134 agnd 135 agnd 136 avdd 137 rx0- 138 rx0+ 139 avdd 140 agnd 141 gnd 142 tx1- 143 tx1+ 144 signal name pin number 16-bit utopia 2 mode[1,0] = 00 8-bit utopia 1 mode[1,0] = 01 dpi mode[1,0] = 10 table 3 signal assignment as a function of phy/atm interface mode (part 4 of 4)
11 of 49 december 2004 IDT77V1264l200 functional description transmission convergence (tc) sub layer introduction the tc sub layer defines the line coding, scrambling, data framing and synchronization. under control of a switch interface or segmenta- tion and reassembly (sar) unit, the 25.6mbps atm phy accepts a 53- byte atm cell, scrambles the data, appends a command byte to the beginning of the cell, and encodes the entire 53 bytes before transmis- sion. these data transformations ensur e that the signal is evenly distrib- uted across the frequency spectrum. in addition, the serialized bit stream is nrzi coded. an 8khz timing sync pulse may be used for isochronous communications. data structure and framing each 53-byte atm cell is preceded with a command byte. this byte is distinguished by an escape symbol followed by one of 17 encoded symbols. together, this byte forms one of seventeen possible command bytes. three command bytes are defined: 1. x_x (read: 'escape' symbol followed by another 'escape'): start- of-cell with scrambler/descrambler reset. 2. x_4 ('escape' followed by '4'): start-of-cell without scrambler/ descrambler reset. 3. x_8 ('escape' followed by '8'): 8khz timing marker. this command byte is generated when the 8khz sync pulse is detected, and has priority over all line activity (data or command bytes). it is transmitted immediately when the sync pulse is detected. when this occurs during a cell transmission, the data transfer is temporarily interrupted on an octet boundary, and the x_8 command byte is inserted. this condition is the only allowed interrupt in an otherwise contiguous transfer. below is an illustration of the cell structure and command byte usage: {x_x} {53-byte atm cell} {x_4} {53-byte atm {x_8} cell}... in the above example, the first atm cell is preceded by the x_x start- of-cell command byte which resets both the transmitter-scrambler and receiver-descrambler pseudo-random nibble generators (prng) to their initial states. the following cell illustrates the insertion of a start-of-cell command without scrambler/descrambler reset. during this cell's trans- mission, an 8khz timing sync pulse triggers insertion of the x_8 8khz timing marker command byte. transmission description refer to figure 4. cell transmission begins with the phy-atm inter- face. an atm layer device transfers a cell into the 77v1264l200 across the utopia transmit bus or dpi transmit bus. this cell enters a 3-cell deep transmit fifo. once a complete cell is in the fifo, transmission begins by passing the cell, four bits (msb first) at a time to the 'scram- bler'. the 'scrambler' takes each nibble of data and exclusive-ors them against the 4 high order bits (x(t), x(t-1), x(t-2), x(t-3)) of a 10 bit pseudo-random nibble generator (prng). its function is to provide the appropriate frequency distribution for the signal across the line. the prng is clocked every time a nibble is processed, regardless of whether the processed nibble is part of a data or command byte. note however that only data nibbles are scrambled. the entire command byte (x _c) is not scrambled before it's encoded (see diagram for illustra- tion). the prng is based upon the following polynomial: x 10 + x 7 + 1 with this polynomial, the four output data bits (d3, d2, d1, d0) will be generated from the following equations: d3 = d3 xor x(t-3) d2 = d2 xor x(t-2) d1 = d1 xor x(t-1) d0 = d0 xor x(t) the following nibble is scrambled with x(t+4), x(t+3), x(t+2), and x(t+1). a scrambler lock between the transmitter and receiver occurs each time an x_x command is sent. an x_x command is initiated only at the beginning of a cell transfer after the prng has cycled through all of its states (2 10 - 1 = 1023 states). the first valid atm data cell transmitted after power on will also be accompanied with an x_x command byte. each time an x_x command byte is sent, the first nibble after the last escape (x) nibble is xor'd with 1111b (prng = 3ffx). because a timing marker command (x_8) may occur at any time, the possibility of a reset prng start-of-cell command and a timing marker command occurring consecutively does exist (e.g. x_x_x_8). in this case, the detection of the last two consecutive escape (x) nibbles will cause the prng to reset to its initial 3ffx state. therefore, the prng is clocked only after the first nibble of the second consecutive escape pair. once the data nibbles have been scrambled using the prng, the nibbles are further encoded using a 4b/5b process. the 4b/5b scheme ensures that an appropriate number of signal transitions occur on the line. a total of seventeen 5-bit symbols are used to represent the sixteen 4-bit data nibbles and the one escape (x ) nibble. the table below lists the 4-bit data with their corresponding 5-bit symbols: this encode/decode implementation has several very desirable prop- erties. among them is the fact that the output data bits can be repre- sented by a set of relatively simple symbols; ! run length is limited to <= 5; ! disparity never exceeds +/- 1. on the receiver, the decoder determines from the received symbols whether a timing marker command (x_8) or a start-of-cell command was sent (x_x or x_4). if a start-of-cell command is detected, the next 53 bytes received are decoded and forwarded to the descrambler. (see tc receive block diagram, figure 5). data 0000 0100 1000 1100 symbol 10101 00111 10010 10111 symbol 01001 01101 11001 11101 data 0001 0101 1001 1101 symbol 01010 01110 11010 11110 data 0010 0110 1010 1110 data 0011 0111 1011 1111 esc(x) = 00010 3505 drw 05a symbol 01011 01111 11011 11111 . .
12 of 49 december 2004 IDT77V1264l200 the output of the 4b/5b encoder provides serial data to the nrzi encoder. the nrzi code transitions the wire voltage each time a '1' bit is sent. this, together with the pr evious encoding schemes guarantees that long run lengths of either '0' or '1's are prevented. each symbol is shifted out with its most significant bit sent first. when no cells are available to transmit, the 77v1264l200 keeps the line active by continuing to transmit valid symbols. but it does not transmit another start-of-cell command until it has another cell for trans- mission. the 77v1264l200 never generates idle cells. transmit hec byte calculation/insertion byte #5 of each atm cell, the hec (header error control) is calcu- lated automatically across the first 4 bytes of the cell header, depending upon the setting of bit 5 of registers 0x03, 0x13, 0x23 and 0x33. this byte is then either inserted as a replacement of the fifth byte transferred to the phy by the external system, or the cell is transmitted as received. a third operating mode provides for insertion of "bad" hec codes which may aid in communication diagnostics. these modes are controlled by the led driver and hec status/control registers. receiver description the receiver side of the tc sublayer operates like the transmitter, but in reverse. the data is nrzi decoded before each symbol is reassem- bled. the symbols are then sent to the 5b/4b decoder, followed by the command byte interpreter, de-scrambler, and finally through a fifo to the utopia or dpi interface to an atm layer device. atm cell format note that although the IDT77V1264l200 can detect symbol and hec errors, it does not attempt to correct them. upon reset or the re-connect, each port's receiver is typically not symbol-synchronized. when not symbol- synchronized, the receiver will indicate a significant number of bad symbols, and will deassert the good signal bit as described below. synchronization is established immedi- ately once that port receives an escape symbol, usually as part of the start-of-cell command byte preceding the first received cell. bit 7 bit 0 header byte 1 header byte 2 header byte 3 header byte 4 udf payload byte 1 ? ? ? payload byte 48 3505 drw 52 udf = user defined field (or hec) . the IDT77V1264l200 monitors line conditions and can provide an interrupt if the line is deemed 'bad'. the interrupt status registers (registers 0x01, 0x11, 0x21 and 0x31) contain a good signal bit (bit 6, set to 0 = bad signal initially) which shows the status of the line per the following algorithm: to declare 'good signal' (from "bad" to "good") there is an up-down counter that counts from 7 to 0 and is initially set to 7. when the clock ticks for 1,024 cycles (32mhz clock, 1,024 cycles = 204.8 symbols) and no "bad symbol" has been received, the counter decreases by one. however, if at least one "bad symbol" is detected during these 1,024 clocks, the counter is increased by one, to a maximum of 7. the good signal bit is set to 1 when this counter reaches 0. the good signal bit could be set to 1 as quickly as 1,433 symbols (204.8 x 7) if no bad symbols have been received. to declare 'bad signal' (from "good" to "bad") the same up-down counter counts from 0 to 7 (being at 0 to provide a "good" status). when the clock ticks for 1,024 cycles (32mhz clock, 1,024 cycles = 204.8 symbols) and there is at least one "bad symbol", the counter increases by one. if it detects all "good symbols" and no "bad symbols" in the next time period, the counter decreases by one. the "bad signal" is declared when the counter reaches 7. the good signal bit could be set to 0 as quickly as 1,433 symbols (204.8 x 7) if at least one "bad symbol" is detected in each of seven consecutive groups of 204.8 symbols. 8khz timing marker the 8khz timing marker, described earlier, is a completely optional feature which is essential for some applications requiring synchroniza- tion for voice or video, and unnecessary for other applications. figure 7 shows the options available fo r generating and receiving the 8khz timing marker. the source of the marker is programmable in the rxref and txref control register (0x40). each port is individually programmable to either a local source or a looped remote source. the local source is txref , which is an 8khz clock of virtually any duty cycle. when unused, txref should be tied high. also note that it is not limited to 8khz, should a different frequency be desired. when looped, a received x_8 command byte causes one to be generated on the transmit side. a received x_8 command byte causes the 77v1264l200 to issue a negative pulse on rxref . the source channel of the marker is programmable. when the clock multiplier in the enhanced control 2 register(s) is set to 2x or 4x, it is also necessary to set the rxref pulse width select in the led driver and hec status/control register(s) to any value greater than the default for proper operation of rxref .
13 of 49 december 2004 IDT77V1264l200 figure 2 block diagram for utopia level 1 configuration (mode[1:0] = 01) rxclk clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 0 rx port 0 clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 1 rx port 1 clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 2 rx port 2 clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 3 rx port 3 utopia multi-phy interface microprocessor interface txdata[7:0] txclk txen [3:0] rxdata[7:0] rxen [3:0] int rst rd wr ale ad[7:0] 4 4 rxled [ 3:0 ] txled [ 3:0 ] rxref txref + - + - + - + - + - + - txsoc txclav[3:0] txparity cs mode[1:0] rxsoc rxclav[3:0] rxparity 3505 drw 03 + - + - osc .
14 of 49 december 2004 IDT77V1264l200 figure 3 block diagram for dpi configuration (mode[1:0] = 10) figure 4 tc transmit block diagram clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 0 rx port 0 clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 1 rx port 1 clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 2 rx port 2 clock recovery 5b/4b encoding/ decoding p/s and s/p nrzi scrambler/ descrambler tx/rx atm cell fifo tx port 3 rx port 3 microprocessor interface p0_tfrm 4 4 rxled[3:0] txled[3:0] rxref txref + - + - + - + - + - + - p0_rd[3:0] p0_tclk mode[1:0] 3505 drw 04 + - + - p0_rfrm p0_rclk p0_td[3:0] int rst rd wr ale ad[7:0] cs dpiclk osc p1_tfrm p1_rd[3:0] p1_tclk p1_rfrm p1_rclk p1_td[3:0] p2_tfrm p2_rd[3:0] p2_tclk p2_rfrm p2_rclk p2_td[3:0] p3_tfrm p3_rd[3:0] p3_tclk p3_rfrm p3_rclk p3_td[3:0] dpi multi-phy interface . phy-atm interface control, hec gen. & insertion scrambler 4 command byte insertion 4 prng 4 scramble nibble next reset 4b/5b encoding 4 nrzi encoding 1 tx + tx - osc clock input txref (8khz) 3505 drw 05 3 cells start of cell utopia or dpi interface
15 of 49 december 2004 IDT77V1264l200 phy-atm interface the 77v1264l200 phy offers three choices in interfacing to atm layer devices such as segmentation and reassembly (sar) and switching chips. mode[1:0] are used to select the configuration of this interface, as shown in the table below. utopia is a physical layer to atm layer interface standardized by the atm forum. it has separate transmit and receive channels and specific handshaking protocols. utopia level 2 has dedicated address signals for both the transmit and receive directions that allow the atm layer device to specify with which of the four phy channels it is commu- nicating. utopia level 1 does not have address signals. instead, key handshaking signals are duplicated so that each channel has its own signals. in both versions of utopia, all channels share a single transmit data bus and a single receive data bus for data transfer. dpi is a low-pin count physical layer to atm layer interface. the low-pin count characteristic allows the 77v1264l200 to incorporate four separate dpi 4-bit ports, one for each of the four serial ports. as with the utopia interfaces, the transmit and receive directions have their own data paths and handshaking. utopia level 2 interface option the 16-bit utopia level 2 interface operates as defined in atm forum document af-phy-0039. this phy-atm interface is selected by setting the mode[1:0] pins both low. this mode is configured as a singl e 16-bit data bus in the transmit (atm-to-phy) direction, and a single 16-bit data bus in the receive (phy-to-atm) direction. in addition to the data bus, each direction also includes a single optional parity bit, an address bus, and several hand- shaking signals. the utopia address of each channel is determined by bits 4 to 0 in the enhanced control registers. please note that the transmit bus and the receive bus operate completely independently. the utopia 2 signals are summarized below: txdata[15:0] atm to phy txparity atm to phy txsoc atm to phy txaddr[4:0] atm to phy txen atm to phy txclav phy to atm txclk atm to phy rxdata[15:0] phy to atm rxparity phy to atm rxsoc phy to atm rxaddr[4:0] atm to phy to determine if any of them has room to accept a cell for transmis- sion (txclav), or has a receive cell available to pass on to the atm device (rxclav). to poll, the atm device drives an address (txaddr or rxaddr) then observes txclav or rxclav on the next cycle of txclk or rxclk. a port must tri-state txclav and rxclav except when it is addressed. if txclav or rxclav is asserted, the atm device may select that port, then transfer a cell to or from it. selection of a port is performed by driving the address of the desired port while txen or rxen is high, then driving txen or rxen low. when txen is driven low, txsoc (start of cell) is driven high to indicate that the first 16 bits of the cell are being driven on txdata. the atm device may chose to temporarily suspend transfer of the cell by deasserting txen . otherwise, txen remains asserted as the next 16 bits are driven onto txdata with each cycle of txclk. in the receive direction, the atm device selects a port if it wished to receive the cell that the port is holding. it does this by asserting rxen . the phy then transfers the data 16 bits each clock cycle, as deter- mined by rxen . as in the transmit direction, the atm device may suspend transfer by deasserting rxen at any time. note that the phy asserts rxsoc coincident with the first 16 bits of each cell. txparity and rxparity are parity bits for the corresponding 16- bit data fields. odd parity is used. figures 9 through 14 may be referenced for utopia 2 bus examples. because this interface transfers an even number of bytes, rather than the atm standard of 53 bytes, a filler byte is inserted between the 5-byte header and the 48-byte payload. this is shown in figure 8. rxen atm to phy rxclav phy to atm rxclk atm to phy
16 of 49 december 2004 IDT77V1264l200 figure 5 tc receive block diagram utopia level 1 multi-phy interface option the utopia level 1 multi-phy interface is based on atm forum docum ent af-phy-0017. utopia level 1 is essentially the same as ut opia level 2, but without the addressing, polling and selection features. figure 6 utopia level 2 data format and sequence instead of addressing, this mode utilizes separate txclav, txen , rxclav and r xe n signals for each channel of the 77v1264l200. there are just one each of the txsoc and rxsoc signals, which are shared across all four channels. in addition to utopia level 2's cell mode transfer protocol, utopia level 1 also offers the option of a byte mode protocol. bit 1 of the master control registers is used to program whether the utopia level 1 bus is in cell mode or byte mode. in byte mode, the phy is allowed to c ontrol data transfer on a byte-by-byte basis via the txclav and rxclav signals. in cell mode, txclav and rxclav are ignored once the transfer of a c ell has begun. in every other way the two modes are identical. cell m ode is the default configuration and is the one described later. 4 phy-atm interface control - recv 4 5 nrzi decoding rx + rx 4 4 prng scramble nibble next reset rxref 32.0mhz clock synthesizer &pll 5b/4b decoding command byte detection, removal, & decode de- scrambler 3505 drw 06 osc 3cells startofcell utopia or dpi interface . clock recovery header byte 1 header byte 3 header byte 5 payloadbyte1 payloadbyte3 payloadbyte5 payload byte 45 header byte 2 header byte 4 stuff byte payload byte 2 payload byte 4 payload byte 6 payload byte 46 payload byte 47 payload byte 48 bit 15 bit 0 first last
17 of 49 december 2004 IDT77V1264l200 figure 7 rxref and txref block diagram the utopia 1 signals are summarized below: txdata[7:0] atm to phy txparity atm to phy txsoc atm to phy txen [3:0] atm to phy txclav[3:0] phy to atm txclk atm to phy rxdata[7:0] phy to atm rxparity phy to atm rxsoc phy to atm rxen [3:0] atm to phy rxclav[3:0] phy to atm rxclk atm to phy idt77v1254 rxref#0 (x_8 received) txref#0 (x_8 generator) txref#1 (x_8 generator) 3505 drw 0 rxref output mux ltsel#0 rxref#1 (x_8 received) mux rxref#2 (x_8 received) mux rxref#3 (x_8 received) mux ltsel#1 ltsel#2 ltsel#3 txref#3 (x_8 generator) txref#2 (x_8 generator) rxrefsel[1:0] rxref select decoder txref input ( reg 40, bit 0) ( reg 40, bit 1) ( reg 40, bit 2) ( reg 40, bit 3) . IDT77V1264l200
18 of 49 december 2004 IDT77V1264l200 transmit and receive both utilize free running clocks, which ar e inputs to the 77v1264l200. all utopia signals are timed to the se clocks. in the transmit direction, the phy first asserts txclav (transmit cell available) to indicate that it has room in its transmit fifo to accept at least one 53-byte atm cell. when the atm layer device is ready to begin passing the cell, it asserts txen (transmit enable) and txsoc (start of cell), coin- cident with the first byte of the cell on txdata. txen remains asserted for the duration of the cell transfer, but the atm device may deassert txen at any time once the cell transfer has begun, but data is transferred only when txen is asserted. in the receive direction, rxen indicates when the atm device is prepared to receive data. as with transmit, it may be asserted or deasserted at any time. note, however, that not more than one rxen should be asserted at a time. also, once a given rx port is selected, that port's fifo must be emptied of cells (as indicated by rxclav) before a different rx port may be enabled. in both transmit and receive, txsoc and rxsoc (start of cell) is asserted for one clock, coincident with the first byte of each cell. odd parity is utilized across each 8-bit data field. figure 8 shows the data sequence for an atm cell over utopia lev el 1, and figures 15 through 21 are examples of the utopia lev el 1 handshake. figure 8 utopia 1 data format and sequence header byte 1 header byte 3 header byte 5 payload byte 1 payload byte 3 header byte 2 header byte 4 payload byte 2 payload byte 46 payload byte 47 payload byte 48 bit 7 bit 0 3505 drw 15 first last .
19 of 49 december 2004 IDT77V1264l200 figure 9 utopia 2 transmit handshake - back to back cells figure 10 utopia 2 transmit handshake - delay between cells txclk txsoc txclav txen txdata[15:0], txparity p39, 40 p41, 42 p43, 44 p45, 46 p47, 48 h1, 2 h3, 4 h5, undefined 3505 drw 09 txaddr[4:0] 1f n+3 1f n+2 1f n+3 1f n 1f n+3 n+2 n+3 n n+1 phy n phy n+3 cell transmission to: polling polling polling: selection p1, 2 high-z . txclk txsoc txclav txen txdata[15:0], txparity p43, 44 p45, 46 p47, 48 h1, 2 h3, 4 h5, undefined 3505 drw 10 txaddr[4:0] 1f n+3 1f n+2 1f n+3 1f n 1f n+3 n+2 n+3 n n+1 phy n phy n+3 cell transmission to: polling polling polling: selection p1, 2 high-z .
20 of 49 december 2004 IDT77V1264l200 figure 11 utopia 2 transmit handshake - transmission suspended figure 12 utopia 2 receive handshake - back to back cells txclk txsoc txclav txen txdata[15:0], txparity p25, 26 p27, 28 p29, 30 p31, 32 p33, 34 3505 drw 11 txaddr[4:0] 1f n+3 1f n+2 1f m 1f n 1f n+3 n+2 m n n+1 phy m phy m cell transmission to: polling polling polling: selection p35, 36 high-z high-z high-z . rxclk rxsoc rxclav rxen rxdata[15:0], rxparity p39, 40 p41, 42 p43, 44 p45, 46 p47, 48 h1, 2 h3, 4 h5, undefined 3505 drw 12 rxaddr[4:0] 1f n+3 1f n+2 1f n+3 1f n 1f n+3 n+2 n+3 n n+1 phy n phy n+3 cell transmission to: polling polling polling: selection p1, 2 high-z high-z high-z .
21 of 49 december 2004 IDT77V1264l200 figure 13 utopia 2 receive handshake - delay between cells figure 14 utopia 2 receive handshake - suspended transfer of data figure 15 utopia 1 transmit handshake - single cell rxclk rxsoc rxclav rxen rxdata[15:0], rxparity p45, 46 p47, 48 h1, 2 h3, 4 3505 drw 13 rxaddr[4:0] n+3 1f n+2 1f n+1 1f n+1 1f n+3 n+2 n+1 n+1 n phy n+3 phy n+1 cell transmission to: polling polling polling: selection undefined 1f high-z high-z high-z . rxclk rxsoc rxclav rxen rxdata[15:0], rxparity p25, 26 p27, 28 p29, 30 p31, 32 p33, 34 3505 drw 14 rxaddr[4:0] n+3 1f n+2 1f m 1f n+1 1f n+3 n+2 m n+1 phy m phy m cell transmission from: polling polling polling: re-selection p35, 36 n+2 high-z high-z high-z txclk txsoc txclav[3:0] txen [3:0] txdata[7:0], txparity x h1 h2 p44 p45 p46 p47 p48 x 3505 drw 16 .
22 of 49 december 2004 IDT77V1264l200 figure 16 utopia 1 transmit handshake - back-to-back cells, and txen suspended transmission figure 17 utopia 1 transmit handshake - txen suspended transmission and back-to-back cells (byte mode only) figure 18 utopia 1 receive handshake - delay between cells txclk txsoc txclav[3:0] txen [3:0] txdata[7:0], txparity p46 p47 p48 h1 h2 h3 h4 x h5 3505 drw 17 3505 drw txclk txsoc txclav[3:0] txen [3:0] txdata[7:0], txparity p42 p43 p44 p45 p46 x x x p47 3505 drw 18 p48 h1 . rxclk rxsoc rxclav[3:0] rxen [3:0] rxdata[7:0], rxparity h1 h2 h3 3505 drw 19 p48 p47 high-z high-z .
23 of 49 december 2004 IDT77V1264l200 figure 19 utopia 1 receive handshake - rxen and rxclav control figure 20 utopia 1 receive handshake - rxclav deassertion figure 21 utopia 1 receive handshake - rxclav suspended transfer (byte mode only) rxclk rxsoc rxclav[3:0] rxen [3:0] rxdata[7:0], rxparity h1 p47 p48 3505 drw 20 p48 p47 high-z high-z x x h1 h2 . rxclk rxsoc rxclav[3:0] rxen [3:0] rxdata[7:0], rxparity p48 x 3505 drw 21 p44 p42 high-z high-z p43 p45 p46 p47 high-z high-z x early rxclav option (bit 6=1, registers 0x02, 0x12, 0x22, 0x32) . rxclk rxsoc rxclav[3:0] rxen [3:0] rxdata[7:0], rxparity h1 h2 x 3505 drw 22 high-z high-z h3 h4 h5 p1 .
24 of 49 december 2004 IDT77V1264l200 dpi interface option the dpi interface is relatively new and worth additional description. the biggest difference between the dpi configurations and the utopia configurations is that each channel has its own dpi interface. each interface has a 4-bit data path, a clock and a start-of-cell signal, for both the transmit direction and the receive direction. therefore, each signal is point-to-point, and none of these signals has high-z capability. addition- ally, there is one master dpi clock input (dpiclk) into the 77v1254l25 which is used as a source for the dpi transmit clock outputs. dpi is a cell-based transfer scheme like utopia level 2, whereas utopia level 1 transfers can be either byte- or cell-based. another unique aspect of dpi is that it is a symmetrical interface. it is as easy to connect two phys back-to-back as it is to connect a phy to a switch fabric chip. in contrast, utopia is asymmetrical. note that for the 77v1254l25 the nomenclature "transmit" and "receive" is used in the naming of the dpi signals, whereas other devices may use more generic "in" and "out" nomenclature for their dpi signals. the dpi signals are summarized below, where "pn_" refers to the signals for channel number "n": in the transmit direction (atm to phy), the atm layer device asserts start-of-cell signal (pn_tfrm) for one clock cycle, one clock prior to driving the first nibble of the cell on pn_td[3:0]. once the atm side has begun sending a cell, it is prepared to send the entire cell without inter- ruption. the 77v1254l25 drives the transmit dpi clocks (pn_tclk) back to the atm device, and can modulate (gap) it to control the flow of data. specifically, if it cannot accept another nibble, the 77v1254l25 disables pn_tclk and does not generate another rising edge until it has room for the nibble. pn_tclk are derived from the dpiclk free running clock source. the dpi protocol is exactly symmetric al in the receive direction, with the 77v1254l25 driving the data and start-of-cell signals while receiving pn_rclk as an input. the dpi data interface is four bits, so the 53 bytes of an atm cell are transferred in 106 cycles. figure 22 shows the sequence of that data transfer. igures 23 through 31 show how the handshake operates. dpiclk input to phy pn_tclk phy to atm pn_td[3:0] atm to phy pn_tfrm atm to phy pn_rclk atm to phy pn_rd[3:0] phy to atm pn_rfrm phy to atm figure 22 dpi data format and sequence header byte 1, (8:5) header byte 1, (4:1) header byte 2, (8:5) header byte 2, (4:1) header byte 3, (8:5) header byte 3, (4:1) header byte 4, (8:5) header byte 4, (4:1) header byte 5, (8:5) header byte 5, (4:1) payload byte 1, (8:5) payload byte 1, (4:1) payload byte 47, (8:5) payload byte 47, (4:1) payload byte 48, (8:5) payload byte 48, (4:1) bit 3 bit 0 first last
25 of 49 december 2004 IDT77V1264l200 figure 23 dpi receive handshake - one cell received figure 24 dpi receive handshake - back-to-back cells figure 25 dpi receive handshake - atm layer device suspends transfer figure 26 dpi receive handshake - neither device ready p_rfrm (out) p_rd(3:0) (out) x cell 1 nibble 0 x x 3505 drw 24 p_rclk (in) x cell 1 nibble 104 cell 1 nibble 105 p_rfrm (out) p_rd(3:0) (out) x cell 1 nibble 0 cell 1 nibble 1 cell 1 nibble 104 cell 1 nibble 105 cell 2 nibble 0 cell 2 nibble 1 3505 drw 25 p_rclk (in) x cell 1 . p_rfrm (out) p_rd(3:0) (out) cell 2 nibble 0 cell 2 nibble 1 cell 2 nibble 2 cell 2 nibble 3 cell 2 nibble 4 3505 drw 26 p_rclk (in) cell 1 nibble 105 cell 1 nibble 104 . p_rfrm (out) p_rd(3:0) (out) xx x cell 2 nibble 0 cell 2 nibble 2 cell 2 nibble 1 3505 drw 27 p_rclk (in) x cell 1 nibble 104 cell 1 nibble 105 atm layer device not ready 77v1254 not ready .
26 of 49 december 2004 IDT77V1264l200 figure 27 dpi transmit handshake - one cell for transmission figure 28 dpi transmit handshake - back-to-back cells for transmission figure 29 dpi transmit handshake - 77v1254l25 transmit fifo full figure 30 dpi transmit handshake - neither device ready p_tfrm (in) p_td(3:0) (in) x cell 1 nibble 0 x x p_tclk (out) x cell 1 nibble 1 cell 1 nibble 104 cell 1 nibble 105 p_tfrm (in) p_td(3:0) (in) x cell 1 nibble 0 cell 1 nibble 1 cell 1 nibble 104 cell 1 nibble 105 cell 2 nibble 0 cell 2 nibble 1 p_tclk (out) x cell 1 p_tfrm (in) p_td(3:0) (in) cell 2 nibble 0 cell 2 nibble 1 cell 2 nibble 2 cell 2 nibble 3 cell 2 nibble 4 p_tclk (out) cell 1 nibble 105 cell 1 nibble 104 p_tfrm (in) p_td(3:0) (in) xx x cell 2 nibble 0 cell 2 nibble 2 cell 2 nibble 1 3505 drw 31 p_tclk (out) x cell 1 nibble 104 cell 1 nibble 105 77v1254 not ready atm layer device not ready .
27 of 49 december 2004 IDT77V1264l200 control and status interface utility bus the utility bus is a byte-wide interface that provides access to the registers within the IDT77V1264l200. these registers are used to select desired operating characteristics and functions, and to communicate status to external systems. the utility bus is implemented using a multiplexed address and data bus (ad[7:0]) where the register address is latched via the address latch enable (ale) signal. the utility bus interface is comprised of the following pins: ad[7:0], ale, cs , rd , wr read operation refer to the utility bus timing waveforms in figures 43 - 44. a register read is performed as follows: 1. initial condition: ?rd , wr , cs not asserted (logic 1) ? ale not asserted (logic 0) 2. set up register address: ? place desired register address on ad[7:0] ? set ale to logic 1; ? latch this address by setting ale to logic 0. 3. read register data: ? remove register address data from ad[7:0] ? assert cs by setting to logic 0; ? assert rd by setting to logic 0 ? wait minimum pulse width ti me (see ac specifications) write operation a register write is performed as described below: 1. initial condition: ?rd , wr , cs not asserted (logic 1) ? ale not asserted (logic 0) 2. set up register address: ? place desired register address on ad[7:0] ? set ale to logic 1; ? latch this address by setting ale to logic 0. 3. write data: ? place data on ad[7:0] ? assert cs by setting to logic 0; ? assert wr (logic 0) for minimum ti me (according to timing specification); reset wr to logic 1 to complete register write cycle. interrupt operations the IDT77V1264l200 provides a variety of selectable interrupt and signalling conditions which are usef ul both during ?normal? operation, and as diagnostic aids. refer to the status and control register list section. overall interrupt control is provided via bit 0 of the master control registers. when this bit is cleared (set to 0), interrupt signalling is prevented on the respective port. the interrupt mask registers allow individual masking of different inte rrupt sources. additional interrupt signal control is provided by bit 5 of the master control registers. when this bit is set (=1), receive cell errors will be flagged via interrupt signal- ling and all other interrupt conditions are masked. these errors include: ! bad receive hec ! short (fewer than 53 bytes) cells ! received cell symbol error normal interrupt operations are performed by setting bit 0 and clearing bit 5 in the master control registers. int (pin 85) will go to a low state when an interrupt condition is detected. the external system should then interrogate the 77v1264l200 to determine which one (or more) conditions caused this flag, and reset the interrupt for further occurrences. this is accomplished by reading the interrupt status registers. decoding the bits in thes e bytes will tell which error condition caused the interrupt. reading these registers also: ! clears the (sticky) interrupt status bits in the registers that are read ! resets int this leaves the interrupt system ready to signal an alarm for further problems. led control and signalling the led outputs provide bi-directional led drive capability of 8 ma. as an example, the rxled outputs are described in the truth table: as illustrated in the following drawing, this could be connected to provide for a two-led condition indica tor. these could also be different colors to provide simple status indication at a glance. (the minimum value for r should be 330 ? ). led indicator txled truth table state pin voltage cells being received low cells not being received high state pin voltage cells being transmitted low cells not being transmitted high rxled(3:0) txled(3:0) 3.3v (indicates: cells being received or transmitted) (indicates: cells are not being received or transmitted) 3505 drw 32 r r
28 of 49 december 2004 IDT77V1264l200 figure 31 dpi transmit handshake - neither device ready diagnostic functions loopback there are two loopback modes supported by the 77v1264l200. the loopba ck mode is controlled via bits 1 and 0 of the diagnostic c ontrol regis- ters: normal mode this mode, figure 32, supports normal operat ing conditions: data to be transmitted is tr ansferred to the tc, where it is queued and formatted for transmission by the pmd. receive data from the pmd is decoded al ong with its clock for transfer to the receiving "upstream syst em". phy loopback as figure 33 illustrates below, this loopback mode provides a connec tion within the phy from the transmit phy-atm interface to the phy-atm receive interface. note that while this mode is operating, no data is forwarded to or received from the line interface. when bi ts [1:0] in the diagnostic control registers are set to 10, the phy loopback mode works only if clock multiplier is 1x. for higher multiplies, these bits must be set to 01. line loopback figure 34 might also be called ?remote loopback? since it provides for a means to test the overall system, including the line. since this mode will probably be entered under direction from another system (at a remote location), receive data is also decoded and transferred to the upstream system to allow it to listen for commands. a common example would be a co mmand asking the upstream system to direct the tc to leave th is loopback state, and resume normal operations. bit 1 bit 0 mode 0 0 normal operating mode 1 0 phy loopback 1 1 line loopback p_tfrm (in) p_td(3:0) (in) xx x cell 2 nibble 0 cell 2 nibble 2 cell 2 nibble 1 3505 drw 31 p_tclk (out) x cell 1 nibble 104 cell 1 nibble 105 77v1254 not ready atm layer device not ready .
29 of 49 december 2004 IDT77V1264l200 figure 32 normal mode figure 33 phy loopback figure 34 line loopback tc sublayer pmd sublayer line interface atm layer device 3505 drw 33 idt77v1254 IDT77V1264l200 atm layer device tc sublayer pmd sublayer line interface 3505 drw 34 idt77v1254 IDT77V1264l200 atm layer device tc sublayer pmd sublayer line interface 3505 drw 35 idt77v1254 IDT77V1264l200
30 of 49 december 2004 IDT77V1264l200 counters several condition counters are provided to assist external systems (e.g. software drivers) in evaluating communications conditions. it is anticipated that these counters will be polled from time to time (user selectable) to evaluate performance. a separate set of registers exists for each channel of the phy. ! symbol error counters ? 8 bits ? counts all invalid 5-bit symbols received ! transmit cell counters ? 16 bits ? counts all transmitted cells ! receive cell counters ? 16 bits ? counts all received cells, excluding idle cells and hec errored cells ! receive hec error counters ? 5 bits ? counts all hec errors received the txcell and rxcell counters are sized (16 bits) to provide a full cell count (without roll over) if the counter is read once/second. the symbol error counter and hec error counter were given sufficient size to indicate exact counts for low error-rate conditions. if these counters overflow, a gross condition is occurring, where additional counter resolu- tion does not provide additional diagnostic benefit. reading counters 1. decide which counter value is desired. write to the counter select register(s) (0x06, 0x16, 0x26 and 0x36) to the bit location corresponding to the desired counter. this loads the high and low byte counter registers with the selected counter?s value, and resets this counter to zero. note: only one counter may be enabled at any time in each of the counter select registers. 2. read the counter registers (0 x04, 0x14, 0x24 or 0x34 (low byte)) and (0x05, 0x15, 0x25 or 0x35 (high byte)) to get the value. further reads may be accomplished in the same manner by writing to the counter select registers. note: the phy takes some time to set up the low and high byte counters after a specific counter has been selected in the counter selector register. this time delay (in s) varies with the line rate and can be calculated as follows: time delay ( s) = 12.5___ line rate (mbps) loop timing feature the 77v1264l200 also offers a loop timing feature for specific appli- cations where data needs to be repeated / transmitted using the recov- ered clock. if the loop timing mode is enabled in the enhanced control register 1 bit 6, the recovered receive clock is used as to clock out data on transmit side. this mode is port specific, i.e., the user can select one or more ports to be in loop timing mode. in normal mode, the transmitter transmits data using the multiplied oscillator clock. jitter in loop timing mode one of the primary concerns w hen using loop timing mode is the amount of jitter that gets added each time data is transmitted. table 4 shows the jitter measured at various data rates. the set-up shown in figure 35 was used to perform these tests. the maximum jitter seen was at tx point 5 and the minimum ji tter was at point 2. the loop timing jitter is defined as the amount of jitter generated by each tx node. in other words, the loop timing jitter or the jitter added by a loop-timed port in the set-up below is the difference between the total output jitter and the total input jitter.
31 of 49 december 2004 IDT77V1264l200 figure 35 test setup for loop timing jitter measurements loop timing jitter specification the waveforms below show some of the measurements taken with the set-up in figure 35. using the formula above, the jitter speci fication was derived. for example, at data rate of 25.6mbps, jitter added going th rough line card 3 is 1.5ns -1.4ns (as shown in the wavefor ms below). line rate mbps data rate mbps min. typ. max. note 32 25.6 -- 100 ps -- using 32mhz osc, multiplier at 1x 64 51.2 -- 100 ps -- using 64mhz osc, multiplier at 1x 128 102.4 -- 80 ps -- using 32mhz osc, multiplier at 4x 256 204.8 -- 20 ps -- using 64mhz osc, multiplier at 4x table 4 loop timing jitter data data data data data data switch loop timing mode loop timing mode loop timing mode p1 p2 p3 clk clk clk rx rx rx tx tx tx tx rx normal mode p0 osc 1 2 3 4 5
32 of 49 december 2004 IDT77V1264l200 jitter at 25.6mbps at point 4 with respect to point 1 jitter at 25.6mbps at point 5 with respect to point 1 jitter at 51.2mbps at point 4 with respect to point 1 jitter at 51.2mbps at point 5 with respect to point 1
33 of 49 december 2004 IDT77V1264l200 from the above measurements taken, the amount of jitter being added at each tx point is not significant. these tests were also run at line rates of 256mbps for extended periods of time (64 hours) and no bit errors were seen. vpi/vci swapping for compatibility with idt's switchstar products (77v400 and 77v500), the 77v1254l25 has the ability to swap parts of the vpi/v ci address space in the header of receive cells. this function is controll ed by the vpi/vci swap bits, which are bit 5 of the enhanced con trol registers (0x08, 0x18, 0x28 and 0x38). the portions of the vpi/vci that are swapped are shown below. bits x(7:0) are swapped with y(7:0) when th e vpi/vci swap bit is set and the chip is in dpi mode. jitter at 102.4mbps at point 4 with respect to point 1 jitter at 102.4mbps at point 5 with respect to point 1 jitter at 256mbps at point 4 with respect to point 1 jitter at 256mbps at point 5 with respect to point 1 byte 0 byte 1 byte 2 byte 3 byte 4 0 7 gfc/vpi vpi vci pti hec vci vci vpi clp byte 0 byte 1 byte 2 byte 3 byte 4 0 7 x7 x6 x5 x4 x3 x2 x1 x0 y3 y2 y1 y0 y7 y6 y5 y4
34 of 49 december 2004 IDT77V1264l200 line side (serial) interface each of the four ports has two pins for differential serial transmission, and two pins for differential serial receiving. phy to magnetics interface a standard connection to 100 ? and 120 ? unshielded twisted pair cabling is s hown in figure 36. note that the transmit signal is somewhat attenu- ated in order to meet the launch amplitude specified by the st andards. the external receive circuitry is designed to attenuate low frequencies in order to compensate for the high frequency attenuation of the cable. also, the receive circuitry biases the positive and negative rx input s to slightly different voltages. this is done so that the receiver does not receive false signals in the absence of a real signal. this can be important because the 77v1264l200 does not disable error detection o r interrupts when an input signal is not present. when connecting to utp at 51.2mbps and 204.8mbps, it is necessary to use magnetics with sufficient bandwidth. refer to table 6 for the recom- mended magnetics. figure 36 recommended connection to magnetics component value tolerance r1 47 ? 5% r2 47 ? 5% r3 620 ? 5% r4 110 ? 5% r5 2700 ? 5% r6 2700 ? 5% r7 82 ? 5% r8 33 ? 5% r9 33 ? 5% table 5 analog component values 7 8 10 9 3 4 5 magnetics r j 4 5 c o n n e c t o r idt77v1253 idt77v1254 agnd 14 13 12 agnd 1 2 16 15 agnd avdd rxd+ rxd- txd+ txd- r1 r2 r3 r4 r5 r8 r9 r7 c1 c2 l1 3505 drw 36 r6 1 2 3 4 5 6 7 8 . IDT77V1264l200
35 of 49 december 2004 IDT77V1264l200 status and control register list the 77v1264l200 has 41 registers that are accessible through the utili ty bus. each of the four ports has 9 registers dedicated to that port. there is only one register (0x40) which is not port specific. for those register bits which control operation of the utopia in terface, the operation of the utopia interface is determined by the registers corre- sponding to the port which is selected at that particular time. for consistent operation, the ut opia control bits should be pro grammed the same for all four ports, except for the utopia 2 port addresses in the enhanced control registers. nomenclature "reserved" register bits, if written, should always be written "0" r/w = register may be read and written via the utility bus r-only or w-only = register is read-only or write-only sticky = register bit is cleared after the register containing it is read ; all sticky bits are read-only ?0? = ?cleared? or ?not set? ?1? = ?set? c1 470pf 20% c2 470pf 20% l1 3.3 h20% magnetics modules for 25.6 mbps pulse pe-67583 or r4005 www.pulseeng.com tdk tla-6m103 www.component.tdk.com magnetics module for 51.2 mbps pulse r4005 www.pulseeng.com magnetics module for 204.8 mbps pulse st6200t www.pulseeng.com table 6 magnetics modules register name register address port 0 port 1 port 2 port 3 all ports master control registers 0x00 0x10 0x20 0x30 interrupt status registers 0x01 0x11 0x21 0x31 diagnostic control registers 0x02 0x12 0x22 0x32 led driver and hec status/control 0x03 0x13 0x23 0x33 low byte counter register [7:0] 0x04 0x14 0x24 0x34 high byte counter register [15:8] 0x05 0x15 0x25 0x35 counter registers read select 0x06 0x16 0x26 0x36 interrupt mask registers 0x07 0x17 0x27 0x37 enhanced control 1 registers 0x08 0x18 0x28 0x38 enhanced control 2 registers 0x09 0x19 0x29 0x39 rxref and txref control register 0x40 component value tolerance table 5 analog component values
36 of 49 december 2004 IDT77V1264l200 master control registers interrupt status registers diagnostic control registers addresses: 0x00, 0x10, 0x20, 0x30 bit type initial state function 7r/w0 reserved 6 r/w 1 = discard errored cells discard receive error cells - on receipt of any cell with an error (e.g. short cell, invalid command mnemonic, receive hec error (if enabled), this cell will be discarded and will not enter the receive fifo. 5 r/w 0 = all interrupts enable cell error interrupts only - if bit 0 in this register is set (interrupts enabled), setting of this bit enables only "received cell error" (as defined in bit 6) to trigger interrupt line. 4 r/w 0 = disabled transmit data parity check - directs tc to check parity of txdata against parity bit located in txparity. 3 r/w 1 = discard idle cells discard received idle cells - directs tc to discard received idle (vpi/vci = 0) cells from pmd without signalling external systems. 2 r/w 0 = not halted halt transmit - halts transmission of data from tc to pmd and forces the txd outputs to the "0" state 1 r/w 0 = cell mode utopia level 1 mode select: - 0 = cell mode, 1 = byte mode. not applicable for utopia 2 or dpi modes. 0 r/w 1 = enable interrupts enable interrupt pin (interrupt mask bit) - enables interrupt output pin (pin 85). if cleared, pin is always high and interrupt is masked. if set, an interrupt will be signaled by setting the interrupt pin to "0". it doesn?t affect the interrupt status registers. addresses: 0x01, 0x11, 0x21, 0x31 bit type initial state function 7reserved 6 r 0 = bad signal good signal bit - see definition on page 14. 1 - good signal 0 - bad signal 5sticky0 hec error cell received - set when a hec error is detected on received cell. 4sticky0 "short cell" received - interrupt signal which flags received cells with fewer than 53 bytes. this condition is detected when receiving start-of-cell command bytes with fewer than 53 bytes between them. 3sticky0 transmit parity error - if bit 4 of register 0x00 / 0x10 / 0x20 / 0x30 is set (transmit data parity check), this interrupt flags a transmit data parity error condition. odd parity is used. 2sticky0 receive signal condition change - this interrupt is set when the received ?signal? changes either from ?bad to good? or from ?good to bad?. 1sticky0 received symbol error - set when an undefined 5-bit symbol is received. 0sticky0 receive fifo overflow - interrupt which indicates when the receive fifo has filled and cannot accept additional data. addresses: 0x02, 0x12, 0x22, 0x32 bit type initial state function 7 r/w 0 = normal force txclav deassert - (applicable only in utopia 1 and 2 modes) used during line loopback mode to prevent upstream system from continuing to send data to the 77v1264l200. not applicable in dpi mode.
37 of 49 december 2004 IDT77V1264l200 led driver and hec status/control registers 6 r/w 0 = utopia rxclav operation select - (for utopia 1 mode) the utopia standard dictates that during cell mode operation, if the receive fifo no longer has a complete cell available for transfer from phy, rxclav is deasserted following transfer of the last byte out of the phy to the upstream system. with this bit set, early deassertion of this signal will occur coinci- dent with the end of payload byte 44 (as in octet mode for txclav). this provides early indication to the upstream system of this impending condition. 0 = "standard utopia rxclav? 1 = "cell mode = byte mode" 5 r/w 1 = tri-state single/multi-phy configuration select - (applicable and writable only in utopia 1 mode) 0 = single: never tri-state rxdata, rxparity and rxsoc 1 = multi-phy mode: tri-state rxdata, rxparity and rxsoc when rxen = 1 4 r/w 0 = normal rflush = clear receive fifo - this signal is used to tell the tc to flush (clear) all data in the receive fifo. the tc signals this completion by clearing this bit. 3 r/w 0 = normal insert transmit payload error - tells tc to insert cell payload errors in transmitted cells. this can be used to test error detection and recovery systems at destination station, or, under loopback control, at the local receiving station. this payload error is accomplished by flipping bit 0 of the last cell payload byte. 2 r/w 0 = normal insert transmit hec error - tells tc to insert hec error in byte 5 of cell. this can be used to test error detection and recovery systems in downstream switches, or, under loopback control, the local receiving station. the hec error is accomplished by flipping bit 0 of the hec byte. 1,0 r/w 00 = normal loopback control bit # 1 0 0 0 normal mode (receive from network) 1 0 phy loopback (with clock recovery) 1 1 1 line loopback 0 1 phy loopback (with clock recovery) 1 1. when bits [1:0] in the diagnostic control registers are set to 10, the phy loopback mode works only if clock multiplier is 1x. for higher multiplies, these bits must be set to 01. addresses: 0x03, 0x13, 0x23, 0x33 bit type initial state function 70 reserved 6 r/w 0 = enable checking disable receive hec checking (hec enable) - when not set, the hec is calculated on first 4 bytes of received cell, and compared against the 5th byte. when set (= 1), the hec byte is not checked. 5 r/w 0 = enable calculate & replace disable transmit hec calculate & replace - when set, the 5th header byte of cells queued for transmit is not replaced with the hec calculated across the first four bytes of that cell. 4, 3 r/w 00 = 1 cycle rxref pulse width select - see notes about 8khz timing marker in the functional description section. bit # 4 3 . 0 0 rxref active for 1 osc cycle 0 1 rxref active for 2 osc cycles 1 0 rxref active for 4 osc cycles 1 1 rxref active for 8 osc cycles 2 r 1 = empty fifo status 1 = txfifo empty 0 = txfifo not empty 1r 1 txled status 0 = cell transmitted 1 = cell not transmitted 0r 1 rxled status 0 = cell received 1 = cell not received addresses: 0x02, 0x12, 0x22, 0x32 bit type initial state function
38 of 49 december 2004 IDT77V1264l200 low byte counter registers [7:0] high byte counter registers [15:8] counter select registers note: for proper operation, only one bit may be set in a counter select register at any time. interrupt mask registers note: when set to "1", these bits mask the corres ponding interrupts going to the interrupt pin (int ). when set to "0", the interrupts are unmasked. these interrupts correspond to the interrupt status bits in the interrupt status registers. addresses: 0x04, 0x14, 0x24, 0x34 bit type initial state function [7:0] r 0x00 provides low byte of counter value selected via registers 0x06, 0x16, 0x26, and 0x36 addresses: 0x05, 0x15, 0x25, 0x35 bit type initial state function [7:0] r 0x00 provides high-byte of counter value selected via registers 0x06, 0x16, 0x26, and 0x36 addresses: 0x06, 0x16, 0x26, 0x36 bit type initial state function 7 ? ? reserved. 6 ? ? reserved. 5 ? ? reserved. 4 ? ? reserved. 3 w 0 symbol error counter. 2 w 0 txcell counter. 1 w 0 rxcell counter. cells with hec errors are never counted. 0 w 0 receive hec error counter. addresses: 0x07, 0x17, 0x27, 0x37 bit type initial state function 70 reserved. 60 reserved. 5 r/w 0 = interrupt enabled hec error cell. 4 r/w 0 = interrupt enabled short cell error. 3 r/w 0 = interrupt enabled transmit parity error. 2 r/w 0 = interrupt enabled receive signal condition change. 1 r/w 0 = interrupt enabled receive cell symbol error. 0 r/w 0 = interrupt enabled receive fifo overflow.
39 of 49 december 2004 IDT77V1264l200 enhanced control 1 registers enhanced control 2 registers rxref and txref control register addresses: 0x08, 0x18, 0x28, 0x38 bit type initial state function 7 w 0 = not reset individual port software reset 1= reset. this bit is self-clearing; it isn?t necessary to write ?0? to exit reset. this bit does not clear the clock multiplier or utopia port address bits. 6r/w0 = osc transmit line clock (or loop timing mode). when set to 0, the osc input is used as the transmit line clock. when set to 1, the recovered receive clock is used as the transmit line clock. 5 r/w 0 = no swap vpi/vci swap dpi mode only. receive direction only. see description earlier. 4-0 r/w port 0 (reg 0x08) 00000 port 1 (reg 0x18) 00001 port 2 (reg 0x28) 00010 port 3 (reg 0x38) 00011 utopia 2 port address when operating in utopia 2 mode, these register bits determine the utopia 2 port address addresses: 0x09, 0x19, 0x29, 0x39 bit type initial state function 7-6 r/w 00 line rate control these bits determine the line bit rate relative to the reference clock, as well as the pre-driver strength for the txd+/- outputs. 00 clock multiplier = 1x, pre-driver strength is ?standard? 01 clock multiplier = 2x, pre-driver strength is ?standard? 10 clock multiplier = 4x, pre-driver strength is ?strong? 11 reserved 5 r/w 0 reserved 4 r/w 0 reserved 3 r/w 0 reserved 2 r/w 0 reserved 1 r/w 0 reserved 0 r/w 0 reserved addresses: 0x40 bit type initial state function 7-6 r/w 0 = rxref 0 (port 0) rxref source select selects which of the four ports (0-3) is the source of rxref . 5 w 0 = not reset master software reset 1 = reset. this bit is self-clearing; it isn?t necessary to write ?0? to exit reset. 40reserved 3-0 r/w 0000 = not looped rxref to txref loop select when set to 0, txref is used to generate x_8 timing marker commands. when set to 1, txref input is ignored, and received x_8 timing commands are looped back and added to the transmit stream of that same port. it is recommended that the rxref pulse width be set to 2x, 4x, and 8x or greater when the clock multiplier is set to 1x, 2x, or 4x respectively and bits 3-0 are set to 1. refer to figure 7. bit 3: port 3 bit 2: port 2 bit 1: port 1 bit 0: port 0
40 of 49 december 2004 IDT77V1264l200 absolute maximum ratings note: stresses greater than those listed under absolute maximum rati ngs may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above t hose indicated in the operati onal sections of this specification is not implied. exposure to absolute maxi mum rating conditions for extended periods may affect reliability. recommended dc operating conditions capacitance (ta = +25c, f = 1mhz) dc electrical characteristics (all pins except tx+/- and rx+/-) symbol rating value unit vterm terminal voltage with respect to gnd -0.5 to +5.5 v tbias temperature under bias -55 to +125 c tstg storage temperature -55 to +120 c iout dc output current 50 ma symbol parameter min. typ. max. unit vdd digital supply voltage 3.13 3.3 3.47 v gnd digital ground voltage 0 0 0 v vih input high voltage 2.0 ____ 5.25 v vil input low voltage -0.3 ____ 0.8 v avdd analog supply voltage 3.13 3.3 3.47 v agnd analog ground voltage 0 0 0 v vdif vdd - avdd -0.5 0 0.5 v symbol parameter conditions max. unit c in 1 1. characterized values, not tested. input capacitance v in = 0v 10 pf c io 1 i/o capacitance v out = 0v 10 pf symbol parameter test conditions min. max. unit i li input leakage current gnd vin vdd -5 5 a i lo /o (as input) leakage current gnd vin vdd -10 10 a v oh1 1 1. for ad[7:0] pins only. output logic "1" voltage i oh = -2ma, vdd = min. 2.4 ? v v oh2 2 2. for all output pins except ad[7:0], int and tx+/-. output logic "1" voltage i oh = -8ma, vdd = min. 2.4 ? v v ol 3 3. for all output pins except tx+/-. output logic "0" voltage i ol = -8ma, vdd = min. ? 0.4 v i dd1 4, 5 4. add 15ma for each tx+/- pair that is driving a load. 5. total supply current is the sum of idd1 and idd2 digital power supply current - vdd osc = 32 mhz, all outputs unloaded ? 91 ma osc = 64 mhz, all outputs unloaded ? 169 ma osc = 256 mhz, all outputs unloaded ? 197 ma i dd2 5 analog power supply current - avdd osc = 32 mhz, all outputs unloaded ? 44 ma osc = 64 mhz, all outputs unloaded ? 54 ma osc = 256 mhz, all outputs unloaded ? 61 ma
41 of 49 december 2004 IDT77V1264l200 dc electrical characteristics (tx+/- output pins only) dc electrical characteristics (rxd+/- input pins only) utopia level 2 bus timing parameters symbol parameter test conditions min. max. unit v oh1 output logic high voltage i oh = -20ma vdd - 0.5v ? v v ol output logic low voltage i ol = -20ma ? 0.5 v symbol parameter min. typ max. unit v ir rxd+/- input voltage range 0 ? vdd v v ip rxd+/- input peak-to-peak differential voltage 0.6 ? 2*vdd v v icm rxd+/- input common mode voltage 1.0 vdd/2 vdd-0.5 v symbol parameter min. max. unit t1 txclk frequency 0.2 50 mhz t2 txclk duty cycle (% of t1) 40 60 % t3 txdata[15:0], txparity setup time to txclk 4 ? ns t4 txdata[15:0], txparity hold time to txclk 1.5 ? ns t5 txaddr[4:0], setup time to txclk 4 ? ns t6 txaddr[4:0], hold time to txclk 1.5 ? ns t7 txsoc, t xe n setup time to txclk 4 ? ns t8 txsoc, t xe n hold time to txclk 1.5 ? ns t9 txclk to txclav high-z 2 10 ns t10 txclk to txclav low-z (min) and valid (max) 2 10 ns t12 rxclk frequency 0.2 50 mhz t13 rxclk duty cycle (% of t12) 40 60 % t14 rxen setup time to rxclk 4 ? ns t15 rxclk hold time to rxclk 1.5 ? ns t16 rxaddr[4:0] setup time to rxclk 4 ? ns t17 rxaddr[4:0] hold time to rxclk 1.5 ? ns t18 rxclk to rxclav high-z 2 10 ns t19 rxclk to rxclav low-z (min) and valid (max) 2 10 ns t20 rxclk to rxsoc high-z 2 10 ns t21 rxclk to rxsoc low-z (min) and valid (max) 2 10 ns t22 rxclk to rxdata, rxparity high-z 2 10 ns t23 rxclk to rxdata, rxparity low-z (min) and valid (max) 2 10 ns
42 of 49 december 2004 IDT77V1264l200 figure 37 utopia level 2 transmit figure 38 utopia level 2 receive 3505 drw 37 txen txclav txdata[15:0], txparity txaddr[4:0] txsoc txclk t 3 t 10 t 7 t 4 t 1 t 2 t 9 t 10 high-z high-z t 8 t 5 t 6 octet 1 octet 2 3505 drw 38 rxen rxclav rxdata[15:0], rxparity rxaddr[4:0] rxsoc rxclk t 19 t 14 t 12 t 13 t 18 t 19 high-z high-z t 15 t 16 t 17 t 21 t 23 t 22 t 20 t 23 t 21 high-z high-z high-z high-z .
43 of 49 december 2004 IDT77V1264l200 utopia level 1 bus timing parameters figure 39 utopia level 1 transmit figure 40 utopia level 1 receive symbol parameter min. max. unit t31 txclk frequency 0.2 50 mhz t32 txclk duty cycle (% of t31) 40 60 % t33 txdata[7:0], txparity setup time to txclk 4 ? ns t34 txdata[7:0], txparity hold time to txclk 1.5 ? ns t35 txsoc, t xe n [3:0] setup time to txclk 4 ? ns t36 txsoc, t xe n [3:0] hold time to txclk 1.5 ? ns t37 txclk to txclav[3:0] invalid (min) and valid (max) 2 10 ns t39 rxclk frequency 0.2 50 mhz t40 rxclk duty cycle (% of t39) 40 60 % t41 r xe n [3:0] setup time to rxclk 4 ? ns t42 r xe n [3:0] hold time to rxclk 1.5 ? ns t43 rxclk to rxclav[3:0] invalid (min) and valid (max) 2 10 ns t44 rxclk to rxsoc high-z 2 10 ns t45 rxclk to rxsoc low-z (min) and valid (max) 2 10 ns t46 rxclk to rxdata, rxparity high-z 2 10 ns t47 rxclk to rxdata, rxparity low-z (min) and valid (max) 2 10 ns 3505 drw 39 txen[3:0] txclav[3:0] txdata[7:0], txparity txsoc txclk t 33 t 37 t 35 t 34 t 31 t 32 t 36 octet 1 octet 2 3505 drw 40 rxen[3:0] rxclav[3:0] rxdata[7:0], rxparity rxsoc rxclk t 41 t 39 t 40 t 43 t 42 t 45 t 47 t 46 t 44 t 47 t 45 high-z high-z high-z high-z
44 of 49 december 2004 IDT77V1264l200 dpi bus timing parameters figure 41 dpi transmit figure 42 dpi receive symbol parameter min. max. unit t51 dpiclk frequency 0.2 50 mhz t52 dpiclk duty cycle (% of t51) 40 60 % t53 dpiclk to pn_tclk propagation delay 2 14 ns t54 pn_tfrm setup time to pn_tclk 4 ? ns t55 pn_tfrm hold time to pn_tclk 1 ? ns t56 pn_td[3:0] setup time to pn_tclk 4 ? ns t57 pn_td[3:0] hold time to pn_tclk 1 ? ns t61 pn_rclk period 25 ? ns t62 pn_rclk high time 10 ? ns t63 pn_rclk low time 10 ? ns t64 pn_rclk to pn_tfrm invalid (min) and valid (max) 2 12 ns t65 pn_rclk to pn_rd invalid (min) and valid (max) 2 12 ns 3505 drw 41 pn_td[3:0] pn_tclk pn_tfrm dpiclk t 54 t 51 t 52 t 55 t 53 t 56 t 57 . 3505 drw 42 pn_rd[3:0] pn_rclk pn_rfrm t 61 t 62 t 64 t 65 t 63 .
45 of 49 december 2004 IDT77V1264l200 utility bus read cycle utility bus write cycle figure 43 utility bus read cycle name min. max. unit description tas 10 ? mhz address setup to ale tcsrd 0 ? % chip select to read enable tah 5 ? ns address hold to ale tapw 10 ? ns ale min pulse width ttria 0 ? ns address tri-state to rd assert trdpw 20 ? ns min. rd pulse width tdh 0 ? ns data valid hold time tch 0 ? ns rd deassert to cs deassert ttrid ? 10 ns rd deassert to data tri-state trd ? 18 ns read data access tar 5 ? ns ale low to start of read trdd 0 ? ns start of read to data low-z name min. max. unit description tapw 10 ? ns ale min pulse width tas 10 ? ns address set up to ale tah 5 ? ns address hold time to ale tcswr 0 ? ns cs assert to wr twrpw 20 ? ns min. wr pulse width tdws 20 ? ns write data set up tdwh 10 ? ns write data hold time tch 0 ? ns wr deassert to cs deassert taw 20 ? ns ale low to end of write 3505 drw 43 cs rd ale tah tas tapw tch trdd trdpw ad[7:0] (output) tdh trd ttrid tcsrd address data tar ad[7:0] (input)
46 of 49 december 2004 IDT77V1264l200 figure 44 utility bus write cycle osc, rxref , txref and reset timing figure 45 osc, rxref , txref and reset timing symbol parameter min. typ. max. unit tcyc osc cycle period 30 15 31.25 15.625 33 16.5 ns ns tch osc high tim 40 ? 60 % tcl osc low time 40 ? 60 % tcc osc cycle to cycle period variation ? ? 1 % trrpd 1 1. the width of the rxref pulse is programmable in the led driver and hec status/control registers. osc to rxref propagation delay 1 ? 30 ns ttrh txref high time 35 ? ? ns ttrl txref low time 35 ? ? ns trspw minimum rst pulse width two osc cycles ? ? ? 3505 drw 44 cs wr ale ad[7:0] tah tas tapw tch tdwh tdws twrpw address data (input) taw tcswr 3505 drw 45 osc rxref trrpd rst trspw txref ttrl trrpd ttrh tcyc tch tcl .
47 of 49 december 2004 IDT77V1264l200 ac test conditions figure 46 output load a note about figures 47 and 48: the atm forum and itu-t standards fo r 25 mbps atm define "network" and "user" interfaces. they are identical except that transmit and receive are switched between the two. a network device can be connected directly to a user device with a straight-through cable. user-to-user or network-to-network connections require a cable with 1-to-7 and 2-to-8 crossovers. figure 47 pc board layout for atm network note: 1.no power or ground plane inside this area. 2.analog power plane inside this area. 3.digital power plane inside this area. 4.a single ground plane should extend over the area cover ed by the analog and digital power planes, without breaks. 5.all analog signal traces should avoid 90 corners. input pulse levels gnd to 3.0v input rise/fall times 3ns input timing reference levels 1.5v output reference levels 1.5v output load see figure 46 900 ? 1.2k ? 3.3v 30pf* * includes jig and scope capacitances. d.u.t. magnetics 1 2 3 4 5 6 7 8 9 10111213141516 rj45 connector 1 2 7 8 agnd tx3+ tx3- idt 77v1254 note 1 note 2 rx filter tx filter 3505 drw 47 rx tx 106 105 141 142 112 111 agnd note 5 rj45 magnetics rj45 magnetics rj45 magnetics 114 115 rx3+ rx3- note 3 . IDT77V1264l200
48 of 49 december 2004 IDT77V1264l200 figure 48 pc board layout for atm user note: 1.no power or ground plane inside this area. 2.analog power plane inside this area. 3.digital power plane inside this area. 4.a single ground plane should extend over the area cover ed by the analog and digital power planes, without breaks. 5.all analog signal traces should avoid 90 corners. package dimensions psc-4053 is a more comprehensive package outline drawing which is available from the packaging section of the idt web site. magnetics 1 2 3 4 5 6 7 8 9 10111213141516 rj45 connector 1 2 7 8 agnd tx3+ tx3- idt 77v1254 note 1 note 2 tx filter rx filter 3505 drw 48 tx rx 106 105 141 142 112 111 agnd note 5 rj45 magnetics rj45 magnetics rj45 magnetics 114 115 rx3+ rx3- note 3 . IDT77V1264l200 2.4792 ' 1 144 a1 a2 e b 144-pin pqfp l 5.5125 ' d 4.4319 ' d1 a 4.3514 ' 5.4035 ' e1 e a a1 a2 d d1 e e1 l e b - 0.25 3.20 - - - - 0.73 - 0.22 3.70 0.33 3.37 31.20 28.00 31.20 28.00 0.88 0.65 - 4.07 - 3.60 - - - - 1.03 - 0.38 symbol min. nom. max. dimensions are in millimeters 37 36 72 73 108 109 3505 drw 49 .
49 of 49 december 2004 IDT77V1264l200 corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-6116 fax: 408-492-8649 www.idt.com for tech support: email: phyhelp@idt.com phone: 408-330-1552 ordering information revision history september 20, 2001 : initial publication. december 6, 2001 : added dpi information. december 9, 2004: removed commerical temperature range throughout datasheet, updated idt logo and datasheet to current template. package idt nnnnn device type a power nnn speed a a process/ temp. range blank 200 25.6 - 204.8 mb/s 77v1254 quad 25mb/s atm phy transmission convergence (tc) and pmd sublayers commercial (0c to +70c) 3505 drw 50 200 l pg 144-pin pqfp (pu-144) i industrial (-40c to +85c) . 77v1264l200

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